1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a shallow trench isolation (STI) structure with a prevention of dishing phenomenon.
2. Description of Related Art
An isolation structure is used to prevent carriers from drifting between two adjacent devices, such as metal-oxide semiconductor (MOS) transistors, through a semiconductor substrate, on which the MOS transistors are formed. So, a charge leakage occurring on the MOS transistors is also avoided. As device integration continuously increases and line width continuously decreases, the fabrication process has achieved to a fabrication level of 0.25 microns or less. At this fabrication level, using STI structure for the isolation purpose becomes a necessary strategy. A STI structure, typically, is formed by patterning a semiconductor substrate by photolithography and anisotropic etching to form a shallow trench in the substrate, and filling the trench with insulating material.
When fabrication level reaches to about 0.25 microns or less, a chemical mechanical polishing (CMP) process is also widely used to globally planarize or polish the structures formed over the substrate. The STI structure conventionally needs the CMP process to polish undesired insulating material deposited on the substrate. However, the CMP process also causes a dishing issue.
FIG. 1A and FIG. 1B are cross-sectional views of a portion of a substrate, schematically illustrating a conventional fabrication process to form a STI structure. In FIG. 1A, a pad oxide layer 12 is formed on a semiconductor substrate 10. A silicon nitride layer 14 is formed on the pad oxide layer 12. Patterning the silicon nitride layer 14, the pad oxide layer 12, and the substrate 10 forms a trench 15a and a trench 15b in the substrate 10, in which the trench 15b is wider than the trench 15a. An oxide layer 16 is formed over the substrate 10 so that the trenches 15a, 15b are also filled by oxide. The top surface of the oxide layer 16 is not planar due to a concave structure of the trenches 15a, 15b. Several silicon-nitride flat regions 14a, 14b between the trenches 15a, 15b are also simultaneously formed after patterning. The silicon-nitride flat region 14b is wider than the silicon-nitride flat region 14a. The oxide layer 16 is formed by chemical vapor deposition (CVD).
In FIG. 1B, after a densification process is performed on the oxide layer 16, a CMP process, using the silicon nitride layer 14 as a stop point, is performed to planarize the oxide layer 16. A remaining portion of the oxide layer 16 becomes an oxide layer 16a.
While the CMP process is performed, the structure surface of the substrate 10 is pressed onto a rotating polishing pad to achieve a polishing purpose. Since the oxide layer 16 is not planar, the polishing pad may easily get a deformation at a portion above the wider trench 15b. After the CMP process, several issues are very possibly induced.
First, a dishing phenomenon 18 occurs on the oxide layer 16a filled in the wider trench 15b shown in FIG. 1A, Second, there is a residue of the oxide layer 16a left on the wider silicon-nitride flat region 14b. Third, since the substrate 100 includes the siliconnitride flat regions 14a, 14b and the trenches 15a, 15b, all of which have different dimension, it is difficult to obtain a sufficient uniformity of the oxide layer 16a after the CMP process.
Conventionally, in order to completely remove the residue of the oxide layer 16a on the silicon nitride layer 14, a strategy of over-polishing on the silicon nitride layer 14 is applied. If there is the residue of the oxide layer on the silicon nitride, it causes a difficulty to remove the silicon nitride layer later. However, even though the residue of the oxide layer 16a can be completely removed, the dishing phenomenon of the oxide layer 16a is aggravated due to a faster polishing rate of the oxide layer 16a.
Conventionally, in order to solve the dishing issue, a dummy pattern structure is proposed by a conventional method. FIG. 2 is a cross-sectional view of a portion of a substrate, schematically illustrating a dummy pattern structure. In FIG. 2, the like reference number represents the like object. Also referring to FIG. 1A and FIG. 1B, a dummy pattern structure 20 is formed in the wider trench 15b so that the trench 15b is divided into two trenches 15c. In this manner, the width of the trenches 15c has not much difference to the trench 15a. Since the width of the trench 15a is narrowed into the width of the trenches 15c the dishing phenomenon is reduced. The dummy pattern structure 20 can reduce the dishing phenomenon but the difference dimension of the silicon-nitride flat regions 14a, 14b is still not solved yet. This causes the residue of the oxide layer 16a remaining on the silicon-nitride layer 14 can not be uniformly removed.